Functional Verification of a SCI-PHY Level 2 Protocol Engine
نویسندگان
چکیده
In this paper we present our results on verifying the implementation of a SCI-PHY (Saturn Compatible Interface for ATM-PHY devices) Level 2 protocol engine, commercialized by PMC-Sierra, Inc. Using the FormalCheck tool, we first established a proper verification environment, then defined a number of relevant liveness and safety properties, which we checked on an abstracted (8 PHY devices) as well as the original (32 PHY devices) hardware model. Throughout our verification efforts, we uncovered a number of mismatches between the hardware design in VHDL and the SCI-PHY protocol specification. Some of these are pertinent design bugs which were not caught during the simulation process.
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